advanced power dual n-channel enhancement electronics corp. mode power mosfet lower gate charge bv dss 20v bottom exposed dfn r ds(on) 45m lower profile i d 4.5a halogen free & rohs compliant product description absolute maximum ratings symbol units v ds v v gs v i d @t a =25 a i d @t a =70 a i dm a p d @t a =25 w t stg t j symbol value unit rthj-a maximum thermal resistance, junction-ambient 3 90 /w data and specifications subject to change without notice AP6970GN2-HF rating halogen-free product 3.6 20 4.5 storage temperature range continuous drain current 3 @ v gs =4.5v continuous drain current 3 @ v gs =4.5v pulsed drain current 1 1.38 -55 to 150 operating junction temperature range -55 to 150 total power dissipation 1 parameter thermal data 201104121 20 + 12 parameter drain-source voltage gate-source voltage advanced power mosfets from apec provide the designer with the best combination of fast switching, ruggedized device design, ultra low on-resistance and cost-effectiveness. dfn 2x2 s1 g1 d2 d1 g2 s2 s1 g1 d2 s2 g2 d1 d1 d2 s1 g1 d2 s2 g2 d1
electrical characteristics@t j =25 o c(unless otherwise specified) symbol parameter test conditions min. typ. max. units bv dss drain-source breakdown voltage v gs =0v, i d =250ua 20 - - v r ds(on) static drain-source on-resistance 2 v gs =4.5v, i d =4a - - 45 m v gs =2.5v, i d =3a - - 64 m v gs(th) gate threshold voltage v ds =v gs , i d =250ua 0.3 - 1.2 v g fs forward transconductance v ds =5v, i d =4a - 11 - s i dss drain-source leakage current v ds =16v, v gs =0v - - 10 ua i gss gate-source leakage v gs =+ 12v, v ds =0v - - + 30 ua q g total gate charge i d =4a - 4.5 7.2 nc q gs gate-source charge v ds =10v - 0.7 - nc q gd gate-drain ("miller") charge v gs =4.5v - 1.7 - nc t d(on) turn-on delay time v ds =10v - 6 - ns t r rise time i d =1a - 7.5 - ns t d(off) turn-off delay time r g =3.3 ? -11- ns t f fall time v gs =5v - 2.5 - ns c iss input capacitance v gs =0v - 275 440 pf c oss output capacitance v ds =10v - 70 - pf c rss reverse transfer capacitance f=1.0mhz - 60 - pf r g gate resistance f=1.0mhz - 2.8 - source-drain diode symbol parameter test conditions min. typ. max. units v sd forward on voltage 2 i s =1.2a, v gs =0v - - 1.2 v t rr reverse recovery time i s =4a, v gs =0 v , - 16 - ns q rr reverse recovery charge di/dt=100a/s - 8 - nc notes: 1.pulse width limited by max. junction temperature. 2.pulse test 3.surface mounted on 1 in 2 copper pad of fr4 board, t < 10sec ; 250 /w when mounted on min. copper pad. this product is sensitive to electrostatic discharge, please handle with caution. use of this product as a critical component in life support or other similar systems is not authorized. apec does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others. apec reserves the right to make changes without further notice to any products herein to improve reliability, function or design. AP6970GN2-HF 2
a p6970gn2-hf fig 1. typical output characteristics fig 2. typical output characteristics fig 3. on-resistance v.s. gate voltage fig 4. normalized on-resistance v.s. junction temperature fi g 5. forward characteristic o f fig 6. gate threshold voltage v.s. reverse diode junction temperature 3 0 10 20 30 012345 v ds , drain-to-source voltage (v) i d , drain current (a) t a =25 o c 5.0v 4.5v 3.5v 2.5v v g = 2.0v 0 4 8 12 16 20 012345 v ds , drain-to-source voltage (v) i d , drain current (a) t a = 150 o c 5.0v 4.5v 3.5v 2.5v v g = 2.0v 30 40 50 60 70 123456 v gs , gate-to-source voltage (v) r ds(on) (m ) i d =3a t a =25 0.4 0.8 1.2 1.6 2.0 -50 0 50 100 150 t j , junction temperature ( o c) normalized r ds(on) i d =4a v g = 4.5 v 0 1 2 3 4 0 0.2 0.4 0.6 0.8 1 1.2 1.4 v sd , source-to-drain voltage (v) i s (a) t j =25 o c t j =150 o c 0.0 0.4 0.8 1.2 1.6 2.0 -50 0 50 100 150 t j , junction temperature ( o c) normalized v gs(th) (v) i d =250ua
AP6970GN2-HF fig 7. gate charge characteristics fig 8. typical capacitance characteristics fig 9. maximum safe operating area fig 10. effective transient thermal impedance fig 11. switching time waveform fig 12. gate charge waveform 4 q v g 4.5v q gs q gd q g charge 0 2 4 6 8 02468 q g , total gate charge (nc) v gs , gate to source voltage (v) i d =4a v ds =10v 0 100 200 300 400 1 5 9 13172125 v ds , drain-to-source voltage (v) c (pf) f =1.0mh z c iss c oss c rss 0.01 0.1 1 10 100 0.01 0.1 1 10 100 v ds , drain-to-source voltage (v) i d (a) t a =25 o c single pulse 100us 1ms 10ms 100ms 1s dc 0.01 0.1 1 0.0001 0.001 0.01 0.1 1 10 100 1000 t , pulse width (s) normalized thermal response (r thja ) 0.01 0.05 0.1 0.2 duty factor=0.5 single pulse p dm duty factor = t/t peak t j = p dm x r thja + t a r thja = 250 /w t t 0.02 operation in this area limited by r ds(on) t d(on) t r t d(off) t f v ds v gs 10% 90%
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